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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
DRAM
AVAILABLE IN MILITARY SPECIFICATIONS
* MIL-STD-883 * SMD Planned
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
PIN ASSIGNMENT (Top View) 24/28-Pin
1 1 2 2 3 3 4 4 5 5 6 6 9 8 10 9 11 10 12 11 13 12 14 13 28 26 27 25 26 24 25 23 24 22 23 21 20 19 19 18 18 17 17 16 16 15 15 14 VSS DQ4 DQ3 /C/A/S /O/E A9 A8 A7 A6 A5 A4 Vss
FEATURES
* Industry-standard x4 pinout, timing, functions and packages * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * Low power, 1mW standby; 150mW active, typical * All inputs, outputs and clocks are TTL-compatible * Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR) HIDDEN * 2,048-cycle (11 row-, 11 column-addresses) * Extended Data-Out (EDO) PAGE access cycle * 5V-tolerant I/Os (5.5V maximum VIH level)
VCC DQ1 DQ2 /W/E /R/A/S NC A10 A0 A1 A2 A3 VCC
OPTIONS
* Timing 60ns access (Contact Factory) 70ns acess 80ns access * Packages Ceramic SOJ Ceramic LCC Ceramic Gull Wing
MARKING
-6 -7 -8 ECJ EC ECG No. 505 No. 212 No. 603
KEY TIMING PARAMETERS
SPEED -6 -7 -8
tRC 110ns 130ns 150ns tRAC 60ns 70ns 80ns tPC 30ns 35ns 40ns tAA 30ns 35ns 40ns tCAC 15ns 18ns 20ns tCAS 12ns 15ns 20ns
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x4 configuration. The AS4LC4M4 ?R?A/S is used to latch the first 11 bits and ?C?A/S the latter 11 bits. READ and WRITE cycles are selected with the ? W / E input. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of ?W/E or ?C?A/S, whichever occurs last. If ?W/E goes LOW prior to ?C?A/S going LOW, the output pins remain open (High- Z) until the next ?C?A/S cycle, regardless of ?O/E.
AS4LC4M4 Rev. 11/97 DS000022
A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of ?W/E or /C/A/S, whichever occurs last. An EARLY WRITE occurs when ?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or READ-MODIFY-WRITE occurs when ?W/E falls after /C/A/S was taken LOW. During EARLY WRITE cycles, the dataoutputs (Q) will remain High-Z regardless of the state of OE. During LATE WRITE or READ-MODIFY-WRITE cycles, ?/ ?O/E must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping ?O/E LOW, no write will occur, and the data-outputs will drive read data from the accessed location. The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by ?W/E and ?O/E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The FAST PAGE cycle is always initiated with a row-address strobed-in by ?R?A/S followed by a column-address strobed-in by C?A/S. ?C?A/S may ? be toggled-in by holding ?R?A/S LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning R?A/S HIGH terminates the FAST PAGE MODE of operation.
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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EDO PAGE MODE
The AS4LC4M4E8 provides EDO PAGE MODE which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after ?C?A/S returns HIGH. EDO allows ?C?A/S precharge time (tCP) to occur without the output data going invalid. This elimination of ?C?A/S output control allows pipeline READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of ?C?A/S. EDO-PAGE-MODE DRAMs operate similarly to FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after ?C?A/S goes HIGH during READs, provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while ?R?A/S and ?C?A/S are LOW, data will toggle from valid data to High-Z and back to the same valid data. If ?O/E is toggled or pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW, data will transition to and remain High-Z (refer to Figure 1). ?W/E can also perform the function of disabling the output devices under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR'd, ?O/E must be used to disable idle banks of DRAMs. Alternatively, pulsing ?W/E to the idle banks during ?C?A/S high time will also High-Z the outputs. Independent of ?O/E control, the outputs will disable after tOFF, which is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
RAS
V IH V IL
CAS
ADDR
DQ V IOH V IOL
,, ,,, ,,,,, ,,,,, ,,,,, ,,,, , , ,,C , , ,
V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) OLUMN (C) COLUMN (D) OPEN V IH V IL
OE
,,
VALID DATA (A) t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B) t OD t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to Low-Z if tOES is met.
The DQs remain High-Z until the next CAS cycle if tOEHC is met.
The DQs remain High-Z until the next CAS cycle if tOEP is met.
Figure 1 OUTPUT ENABLE AND DISABLE
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
REFRESH
Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle (?R?A/S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of R?AS addresses are executed at least every 32ms, regardless ?/ of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.
RAS
CAS
ADDR
DQ V IOH V IOL
,, ,,, ,,,,,, ,,,,, ,,,,, ,,, , , ,, ,,
V IH V IL V IH V IL V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) OPEN V IH V IL V IH V IL
WE
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE
The DQs go to High-Z if WE falls, and if tWPZ is met, will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated).
Figure 2 ?W/E CONTROL OF DQs
,, ,, , ,,
DON'T CARE UNDEFINED
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
FUNCTIONAL BLOCK DIAGRAM
WE CAS
DATA-IN BUFFER
4
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
4 4
DQ1 DQ2 DQ3 DQ4
OE COLUMNADDRESS BUFFER(11) REFRESH CONTROLLER
COMPLEMENT SELECT
11 11 ROWADDRESS BUFFERS (11) ROW DECODER
ROW SELECT (2 of 4096)
2048 2048 2048 2048
11
2048
4096 x 1024 x 4 MEMORY ARRAY
RAS
NO. 1 CLOCK GENERATOR
ROW TRANSFER ROW TRANSFER (1 OF 2) (1 OF 2) VDD Vss
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
10 1
COLUMN DECODER
1024
4
SENSE AMPLIFIERS I/O GATING
1024 REFRESH COUNTER
TRUTH TABLE
ADDRESSES FUNCTION Standby READ EARLY WRITE READ WRITE EDO-PAGE-MODE READ EDO-PAGE-MODE EARLY-WRITE EDO-PAGE-MODE READ-WRITE HIDDEN REFRESH ?R?A/S-ONLY REFRESH CBR REFRESH
AS4LC4M4 Rev. 11/97 DS000022
DATA-IN/OUT DQ1-DQ4 High-Z Data-Out Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z
?R?A/S H L L L 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle Any Cycle 1st Cycle 2nd Cycle READ WRITE L L L L L L L L>H>L L>H>L L H>L
?C?A/S H>X L L L H>L H>L H>L H>L L>H H>L H>L L L H L
?W/E X H L H>L H H L L H H>L H>L H L X H
?O/E X L X L>H L L X X L L>H L>H L X X X
tR
tC
X ROW ROW ROW ROW n/a ROW n/a n/a ROW n/a ROW ROW ROW X
X COL COL COL COL COL COL COL n/a COL COL COL COL n/a X
2-76
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC pin Relative to VSS ................. -1V to +4.6V Voltage on NC, Inputs or I/O pins Relative to VSS .................................................... -1V to +5.5V Operating Temperature, TA (ambient) .. TA(MIN) = -55C ................................................................... TC (MAX) = 125C Storage Temperature ................................... -55C to +150C Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (VCC = +3.3V 0.3V) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs (including NC pins) Input Low (Logic 0) Voltage, all inputs (including NC pins) INPUT LEAKAGE CURRENT Vcc = 3.6V Any input 0V VIN 5.5V (All other pins not under test = 0V) (NC pins not tested) OUTPUT LEAKAGE CURRENT (Q is disabled; 0V VOUT 5.5V) Vcc=3.6V OUTPUT LEVELS Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) SYMBOL VCC VIH VIL II IOZ VOH VOL MIN 3.0 2.0 -1.0 -2 -10 2.4 0.4 MAX 3.6 VCC+1 0.8 2 10 UNITS V V V A A V V NOTES
MAX PARAMETER/CONDITION STANDBY CURRENT: (TTL) (?R?A/S = ?C?A/S = VIH) STANDBY CURRENT: (CMOS) (?R?A/S = ?C?A/S = other inputs = VCC -0.2V OPERATING CURRENT: Random READ/WRITE Average power supply current (?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: ?R?A/S ONLY Average power supply current (?R?A/S cycling, ?C?A/S = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN]) SYM ICC1 ICC2 -6 2 1 -7 2 1 -8 2 1 UNITS mA mA NOTES
ICC3
120
110
100
mA
3, 4, 12
ICC4
110
100
90
mA
3, 4, 12
ICC5
120
110
100
mA
3, 12
ICC6
120
110
100
mA
3, 5
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
CAPACITANCE
PARAMETER Input Capacitance: Address pins Input Capacitance: ?R?A/S, ?C?A/S, ?W/E, ?O/E Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 7 7 8 UNITS pF pF pF NOTES 2 2 2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER Access time from column-address Column-address set-up to ?C?A/S precharge during write Column-address hold time (referenced to ?R?A/S) Column-address setup time Row-address setup time Column-address to ?W/E delay time Access time from ?C?A/S Column-address hold time ?C?A/S pulse width ?C?A/S hold time (CBR REFRESH) ?C?A/S to output in Low-Z Data output hold after next ?C?A/S LOW ?C?A/S precharge time Access time from ?C?A/S precharge ?C?A/S to ?R?A/S precharge time ?C?A/S hold time ?C?A/S setup time (CBR REFRESH) ?C?A/S to ?W/E delay time Write command to ?C?A/S lead time Data-in hold time Data-in hold time (referenced to ?R?A/S) Data-in setup time Output disable Output Enable OE hold time from WE during READ-MODIFY-WRITE cycle ?/ ?/ ?O/E HIGH hold from ?C?A/S HIGH ?O/E HIGH pulse width ?O/E LOW to ?C?A/S HIGH setup time -6 MIN MAX 30 15 45 0 0 55 15 10 12 10,000 10 0 5 10 35 5 50 5 35 15 10 40 0 0 15 15 10 10 10 5 -7 MIN 15 55 0 0 65 20 15 15 15 0 5 10 5 55 5 40 15 12 56 0 0 12 10 10 5 10,000 15 20 15 0 5 10 5 60 10 45 20 15 55 0 15 20 15 10 10 5 20 20 MAX 35 MIN 20 60 0 0 65 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
SYM tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDHR tDS tOD tOE tOEH tOEHC tOEP tOES
20 14
5
15
40
40
5 20 21 21 22
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER SYM tOFF Output buffer turn-off delay OE setup prior to RAS during HIDDEN REFRESH cycle tORD ?/ ??/ tPC EDO-PAGE-MODE READ or WRITE cycle time tPRWC EDO-PAGE-MODE READ-WRITE cycle time tRAC Access time from ?R?A/S tRAD ?R?A/S to column-address delay time tRAH Row-address hold time tRAL Column-address to ?R?A/S lead time tRAS ?R?A/S pulse width tRASP ?R?A/S pulse width (EDO PAGE MODE) tRC Random READ or WRITE cycle time tRCD ?R?A/S to ?C?A/S delay time tRCH Read command hold time (referenced to ?C?A/S) tRCS Read command setup time tREF Refresh period (2,048 cycles) tRP ?R?A/S precharge time tRPC ?R?A/S to ?C?A/S precharge time tRRH Read command hold time (referenced to ?R?A/S) tRSH ?R?A/S hold time tRWC READ WRITE cycle time tRWD ?R?A/S to ?W/E delay time tRWL Write command to ?R?A/S lead time tT Transition time (rise or fall) tWCH Write command hold time tWCR Write command hold time (referenced to ?R?A/S) tWCS ?W/E command setup time tWHZ Output disable delay from ?W/E tWP Write command pulse width tWPZ ?W/E pulse to disable at ?C?A/S HIGH tWRH ?W/E hold time (CBR REFRESH) tWRP ?W/E setup time (CBR REFRESH) -6 MIN 0 0 30 75 15 10 30 60 60 110 16 0 0 40 5 0 13 150 80 15 2 10 40 0 0 10 10 10 10 MAX 15 MIN 0 0 35 85 15 10 35 70 70 130 16 0 0 50 5 0 15 180 90 15 2 12 56 0 0 12 12 10 10 -7 MAX 15 MIN 0 0 40 90 15 10 40 80 80 150 20 0 0 60 5 0 15 200 105 20 2 15 60 0 0 15 15 10 10 -8 MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 19
60 30
70 35
80 40
13 17
10,000 100,000 45
10,000 100,000 50
10,000 100,00 60
16 18
32
32
32
18
20
30
30
30
20
14
16
20
24 24
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
NOTES
1. 2. 3. 4. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V; f = 1 MHz. ICC is dependent on cycle rates. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the ful temperature range is assured. 7. An initail pause of 100s is required after power-up followed by eight /R/A/S refresh cycles (/R/A/S ONLY or CBR with /W/E HIGH) before proper device operation is assured. The eight /R/A/S cycle wake-ups should be repeated any thime the tREF refresh requirement is exceeded. 8. AC characteristics assume tT = 2.5ns. 9. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. Column address changed once each cycle. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2.0V. 13. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 14. Assumes that tRCD tRCD (MAX). 15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, ?C?A/S must be pulsed HIGH for tCP. 16. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC, provided tRAD is not exceeded. 17. Operation within the tRAD (MAX) limit ensures that tRAC (MIN) and tCAC (MIN) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA, provided tRCD is not exceeded. 18. Either tRCH or tRRH must be satisfied for a READ cycle. 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to VOH or VOL. It is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. 20. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. ?O/E held HIGH and ?W/E taken LOW after ?C?A/S goes LOW results in a LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 21. These parameters are referenced to ?C?A/S leading edge in EARLY WRITE cycles and ?W/E leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 22. If ?O/E is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, ?W/E must be pulsed during ?C?A/S HIGH time in order to place I/O buffers in High-Z. 23. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, ?W/E = LOW and ?O/E = HIGH. 24. tWTS and tWTH are setup and hold specifications for the /W/E pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of tWRP and tWRH in the CBR REFRESH cycle.
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP CAS V IH V IL tRCD tCAS tRRH tRP
RAS
ADDR
WE
DQ
OE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
, ,,, ,,,,, , ,,,,, , , ,, , ,, , ,, ,,,,,,,,,,,,,,,,,, ,, ,, ,, ,
tAR tRAD tRAH tRAL tASR tASC tCAH tACH V IH V IL ROW COLUMN ROW tWRP tWRH tRCS tRCH V IH V IL NOTE 1 tAA tRAC tCAC tCLZ NOTE 2 tOFF V OH V OL OPEN VALID DATA OPEN t OE t OD V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE tOFF
AS4LC4M4 Rev. 11/97 DS000022
-7 MAX 30 MIN 15 50 0 0 15 20 15 15 0 5 55 0 0 10,000 15 20 0 5 60 MAX 35 MIN 20 60 0 0
-8 MAX 40
UNITS
-6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAC tRAD tRAH tRAL tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP MIN 15 10 30 60 110 16 0 0 40 0 10 10 10 MAX 60 30 MIN 15 10 35 70 130 16 0 0 50 0 12 10 10
-7 MAX 70 35 MIN 15 10 40 80 150 20 0 0 60 0 15 10 10
-8 MAX 80 40
UNITS
MIN 15 45 0 0 10 12 0 5 50 0 0
10,000 45
10,000 50
10,000 60
20 10,000
10,000
15 15 15
15 20 15
0
20 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2-81
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,,, ,,, ,,,,, , ,, ,,,,,,, ,,,,,,,,, ,,,,,,, ,,,,,,,,, ,, , , ,,,,,, , ,,,, , , , ,,
tCRP tRCD CAS V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tACH ADDR V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS tWRP tWRH WE V IH V IL NOTE 1 tDHR tDH tDS V DQ V IOH IOL V IH V IL VALID DATA OE
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tACH tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDHR tDS tRAD tRAH MIN 15 45 0 0 10 12 5 50 15 10 40 0 15 10 MAX MIN 15 55 0 0 15 15 5 55 15 12 50 0 15 10 -7 MAX MIN 20 60 0 0 15 20 5 60 20 15 55 0 15 10 -8 UNITS ns ns ns ns ns 10,000 ns ns ns ns ns ns ns 40 ns ns MAX SYM tRAL tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP MIN 30 60 110 16 40 13 15 10 40 0 10 10 10 -6 MAX 10,000 45 -7 MIN MAX 35 70 10,000 130 16 50 50 15 15 12 50 0 12 10 10 -8 MIN 40 80 150 20 60 0 20 15 60 0 15 10 10 MAX 10,000 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000
10,000
30
35
AS4LC4M4 Rev. 11/97 DS000022
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS
ADDR
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,, ,,, ,,,, ,, ,, , , , , , ,, , ,, , ,, ,, ,, , ,, ,, ,,,, ,, ,, , , ,, , , , ,, , , ,
tCRP tRCD CAS V IH V IL tAR tRAD tRAL tASR tRAH tASC tCAH tACH V IH V IL ROW COLUMN ROW tRWD tCWL tRWL tWP tRCS tCWD tWRP tWRH tAWD WE V IH V IL NOTE 1 tAA tRAC tCAC t CLZ tDS tDH V DQ V IOH IOL OPEN VALID D OUT tOD VALID D IN OPEN tOE tOEH OE V IH V IL
,
-7
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS tOD MIN 15 45 0 0 55 15 10 12 0 5 50 35 15 10 0 0 10,000 15 15 0 5 55 40 15 12 0 0 MAX 30 MIN 15 55 0 0 65 20 10,000 15 20 0 5 60 45 20 15 0 0 -7 MAX 35 MIN 20 60 0 0 65 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM MIN tOE tOEH 10 tRAC tRAD 15 tRAH 10 tRAL 30 tRAS 60 tRCD 16 tRCS 0 tRP 40 tRSH 13 tRWC 150 tRWD 80 tRWL 15 tWP 10 tWRH 10 tWRP 10 -6 MAX 15 60 30 MIN 12 15 10 35 70 10,000 16 50 0 50 15 180 90 15 12 10 10 70 35 -8 MAX 20 MIN 15 15 10 40 80 20 0 60 15 200 105 20 15 10 10 80 40 MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000 45
10,000 60
15
15
20
AS4LC4M4 Rev. 11/97 DS000022
2-83
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EDO-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS
CAS
ADDR
WE
DQ
OE
,, ,,, ,,, ,,, ,, ,, ,, ,, , ,,, , ,,,,, , , ,,
V IH V IL tAR tRAD tRAH tACH tACH tASR tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN tWRP tWRH tRCS V IH V IL NOTE 1 tAA tAA tRAC tCAC tCPA tCAC tCLZ tCOH V OH V OL OPEN VALID DATA VALID DATA tOE tOD V IH V IL tOES
tACH tASC
COLUMN
tCLZ
tOEHC
tOEP
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,,,, ,, , ,, , ,,,, , ,, , ,
tRAL tCAH ROW tRCH tAA tRRH tCPA tCAC tOFF VALID DATA OPEN tOE tOD tOES
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE tOEHC MIN 15 45 0 0 15 10 12 0 5 10 5 50 0 10 10,000 15 15 0 5 10 5 55 0 10 MAX 30 MIN 15 55 0 0 20 10,000 15 20 0 5 10 5 60 0 10 -7 MAX 35 MIN 20 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOEP tOES tOFF tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP MIN 10 5 0 30 15 10 30 60 16 0 0 40 0 13 10 10 -6 MAX MIN 10 5 0 35 15 10 35 70 16 0 0 50 0 15 10 10 -7 MAX -8 MIN 10 5 0 40 15 10 40 80 20 0 0 60 0 15 10 10 UNITS ns ns 20 ns ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns ns MAX
15 60 30
15 70 35
100,000 45
100,000 50
35
40
40
15 15
15 20
20 20
AS4LC4M4 Rev. 11/97 DS000022
2-84
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP V IH V IL tCSH tPC tCP tRSH tCAS tCRP tRCD tCAS tCAS tCP tCP tRP
RAS
ADDR
NOTE:
,, , , , , , ,, ,, , , , , , ,, , ,,, ,, ,,,,, ,,,,, , , , ,, ,,,,,,,,,,,,,,,,,,,, ,, , , , ,
CAS V IH V IL tAR tACH tRAD tACH tACH tASR tRAH tASC tCAH tASC tCAH tASC tRAL tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tCWL tWP tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH tWCS tWCH tWRP tWRH WE V IH V IL NOTE 1 tWCR tDHR tDH tRWL tDS tDS tDH tDS tDH V DQ V IOH IOL V IH V IL VALID DATA VALID DATA VALID DATA OE
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tACH tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDHR tDS tPC MIN 15 45 0 0 10 12 10 5 50 15 10 40 0 30 MAX MIN 15 55 0 0 12 15 10 5 55 15 12 50 0 35 -7 MAX MIN 20 60 0 0 15 20 10 5 60 20 15 55 0 40 -8 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAD tRAH tRAL tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP -6 MIN MAX 15 30 10 30 60 100,000 16 45 40 13 15 10 40 0 10 10 10 -7 -8 MIN MAX MIN MAX 15 35 15 40 10 10 35 40 70 100,000 80 100,00 16 50 20 60 50 60 15 15 15 20 12 15 50 60 0 0 12 15 10 10 10 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10,000
10,000
10,000
AS4LC4M4 Rev. 11/97 DS000022
2-85
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH t PC tPRWC NOTE 1 tRSH tCAS tCRP tRCD tCAS tCP tCAS tCP tCP tRP RAS
ADDR
NOTE:
1. is for LATE WRITE cycles only. 2. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
tPC
,, ,,,,,,,, , , ,, , , ,, ,,,, ,, , ,, ,,,,, ,, , ,, ,,,,, , ,, , ,, , ,, ,
CAS V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRWD tRCS tRWL tCWL tWP tAWD tCWD tCWL tWP tAWD tCWD tAWD tCWL tWP tWRP tWRH tCWD WE V IH V IL NOTE 2 tAA tAA tAA tRAC tDH tDS tCPA tDH tDS tCPA tDH tDS tCAC tCLZ tCAC tCLZ tCAC tCLZ DQ V IOH V IOL OPEN
VALID D OUT VALID D IN VALID D OUT VALID D IN VALID D OUT VALID D IN
OPEN
tOD
tOD
tOD
tOE
tOE
tOE
tOEH
OE
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS tOD
AS4LC4M4 Rev. 11/97 DS000022
-7 MAX 30 MIN 55 0 0 65 15 20 15 15 0 10 5 55 40 15 12 0 0 10,000 15 20 0 10 5 60 45 20 15 0 0 MAX 35 MIN 60 0 0 65
-8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOE tOEH tPC tPRWC tRAC tRAD tRAH tRAL tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP tWRH tWRP MIN 10 30 75 15 10 30 60 16 0 40 13 80 15 10 10 10
-6 MAX 15 MIN 12 35 85 60 30
-7 MAX 20 MIN
-8 UNITS ns 15 ns 40 ns 90 ns 80 ns 15 40 ns 10 ns 40 ns 80 100,000 ns 20 60 ns 0 ns 60 ns 15 ns 105 ns 20 ns 15 ns 10 ns 10 ns MAX 20
MIN 45 0 0 55 10 12 0 10 5 50 35 15 10 0 0
20 10,000
10,000
100,000 45
35
40
40
15
15
20
70 15 35 10 35 70 100,000 16 50 0 50 15 90 15 12 10 10
2-86
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP RAS V IH V IL t CSH t PC t CRP V IH V IL t RCD t CAS t CP t CAS t PC t CP t CAS t RSH t CP t RP
,,,,, ,,, ,,, ,, , , , ,, , ,,,,,,, ,,,
CAS t AR t RAD tASR t RAH t ASC t CAH t ASC t CAH ADDR V IH V IL ROW COLUMN (A) COLUMN (B) tWRP tWRH t RCS t RCH WE V IH V IL NOTE 1 t AA t AA t RAC t CPA t CAC t CAC t COH t WHZ DQ V IOH V IOL OPEN VALID DATA (A) VALID DATA (B) t OE OE V IH V IL
t ACH t ASC t CAH
COLUMN (N) t WCS
t WCH
,, ,,
t RAL
ROW
t DS
t DH
VALID DATA IN
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,, , , ,
-7 MAX 70 35 MIN 40 15 10 40 80 20 0 0 60 15 15 0 0 10 10
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS tOE MIN 15 45 0 0 15 10 12 5 10 5 50 10 0 15 10,000 15 15 5 10 5 55 12 0 20 MAX 30 MIN 15 55 0 0 20 10,000 15 20 5 10 5 60 15 0 20 -7 MAX 35 MIN 20 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ tWRH tWRP MIN 30 15 10 30 60 16 0 0 40 13 10 0 0 10 10 -6 MAX 60 30 MIN 35 15 10 35 70 16 0 0 50 15 12 0 0 10 10 UNITS ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns 15 ns ns ns -8 MAX
100,000 45
100,000 50
35
40
40
13
15
AS4LC4M4 Rev. 11/97 DS000022
2-87
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
READ CYCLE (with ?W/E-controlled disable)
RAS V IH V IL tCSH
CAS
ADDR
WE
DQ
OE
NOTE:
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
, ,,, ,,,,, ,, ,, , ,, , , ,,,,,,,,,,,,,,,,, ,, , ,, ,, ,
tCRP tRCD tCAS tCP V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC V IH V IL ROW COLUMN COLUMN tWRP tWRH tRCS tRCH tWPZ tRCS V IH V IL NOTE 1 tAA tRAC tCAC tCLZ tWHZ tCLZ V OH V OL OPEN VALID DATA t OD OPEN t OE V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tOD MIN 45 0 0 15 10 12 0 10 5 50 0 10,000 15 15 0 10 5 55 0 MAX 30 MIN 55 0 0 20 10,000 15 20 0 10 5 60 0 -7 MAX 35 MIN 60 0 0 20 10,000 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYM tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ tWRH tWRP MIN -6 MAX 15 60 30 45 MIN -7 MAX 20 70 35 50 MIN -8 MAX 20 80 40 60 UNITS ns ns ns ns ns ns ns ns ns ns ns
15 10 16 0 0 0 10 10 10
14
15 10 16 0 0 0 12 10 10
16
15 10 20 0 0 0 15 10 10
20
15
15
20
AS4LC4M4 Rev. 11/97 DS000022
2-88
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
?R?A/S-ONLY REFRESH CYCLE
tRC tRAS tRP
AS4LC4M4 883C 4 MEG x 4 DRAM
RAS
CAS
ADDR
V DQ V OH OL
WE
,,, ,,, ,
tCRP V IH V IL V IH V IL V IH V IL
V IH V IL
tASR
ROW
tWRP
NOTE 1
CBR REFRESH CYCLE (Addresses and ?O/E = DON'T CARE)
tRAS tRP
,,,,,,,,, ,,,,,,,, ,,,, ,, , , ,
tRPC tRAH ROW OPEN tWRH tWRP tWRH
tRP RAS V IH V IL tRPC
tRAS
CAS
DQ
WE
NOTE:
,,,,,,,,,,,,,,,,, ,, ,, ,, ,
tCP tCSR tCHR tRPC tCSR tCHR V IH V IL V OH V OL OPEN tWRP tWRH tWRP tWRH V IH V IL
1. Although ?W/E is a "don't care" at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
,
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tASR tCHR tCP tCRP tCSR tRAH MIN 0 10 10 5 5 10 MAX MIN 0 15 10 5 5 10 -7 MAX MIN 0 15 10 5 10 10 -8 MAX UNITS ns ns ns ns ns ns SYM tRAS tRC tRP tRPC tWRH tWRP MIN 60 110 40 5 10 10 -6 MAX 10,000 MIN 70 130 50 5 10 10 -7 MAX 10,000 MIN 80 150 60 5 10 10 -8 MAX 10,000 UNITS ns ns ns ns ns ns
AS4LC4M4 Rev. 11/97 DS000022
2-89
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
HIDDEN REFRESH CYCLE 24 (?W/E = HIGH; ?O/E = LOW)
tRAS RAS V IH V IL tRP tRAS
ADDR
, ,,,,,,,,,,,,, , ,, , , , , , ,,,,,,,, , ,,,, , ,,, ,,,
tCRP tRCD tRSH CAS tCHR V IH V IL tAR tRAD tASR tRAH tASC tRAL tCAH V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V OH OL OPEN VALID DATA OPEN tOE tOD V OE V IH IL tORD
,
MIN 0 0 15 10 40 80 20 60 15
DON'T CARE UNDEFINED
TIMING PARAMETERS
-6 SYM tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD tOE MIN 45 0 0 15 10 10 0 5 0 15 15 0 5 0 MAX 30 MIN 55 0 0 20 15 15 0 5 0 -7 MAX 35 MIN 60 0 0 20 -8 MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns SYM tOFF tORD tRAC tRAD tRAH tRAL tRAS tRCD tRP tRSH MIN 0 0 15 10 30 60 16 40 13 -6 MAX 15 60 30 MIN 0 0 15 10 35 70 16 50 15 -7 MAX 15 70 35 -8 UNITS ns ns 80 ns 40 ns ns ns 10,000 ns 60 ns ns ns MAX 20
10,000 45
10,000 50
15 15
15 20
20 20
AS4LC4M4 Rev. 11/97 DS000022
2-90
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL TEST REQUIREMENTS
AS4LC4M4 883C 4 MEG x 4 DRAM
MIL-STD-883 TEST REQUIREMENTS INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS (Method 5004) FINAL ELECTRICAL TEST PARAMETERS (Method 5004) GROUP A TEST REQUIREMENTS (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS (Method 5005)
SUBGROUPS (per Method 5005, Table I) 2, 8A, 10 1*, 2, 3, 7*, 8, 9, 10, 11 1, 2, 3, 4**, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11
* PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.
AS4LC4M4 Rev. 11/97 DS000022
2-91
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C 4 MEG x 4 DRAM
AS4LC4M4 Rev. 11/97 DS000022
2-92
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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